Many advancements in technology, design automation, and novel applications have fueled the growth of chip design and the VLSI industry significantly. However, apart from the technical aspects, there are many practices followed in the industry which are not "really technical" in the true sense as they are neither functional nor technological needs, but are more "commercial" practices driven from economic and marketing metrics. They are usually not covered in regular classroom courses of VLSI design and form a niche topic, very relevant to the success of the semiconductor industry. I am listing some of these practices which intrigued me when I first learned about them during my tenure at a semiconductor company. I plan to develop this page by adding one topic at a time gradually.
1. Spare gates
Unlike a typical software design where fixing a bug involves a recompilation of the code after changes, the bug fixing methods for a hardware chip still remain the same as earlier. Fixing a hardware bug requires regenerating the mask used for manufacturing the chip, incurring delays and cost of mask regeneration. A chip is designed in multiple layers with the lowest layer being composed of silicon material while higher layers consisting of metal connections. Regenerating the mask for the silicon layer involves significant cost (~Million $) as well as considerable amount of time (3-4 weeks) in comparison to metal layers. With complexity of circuits growing and technology scaling, the chances of a bug being discovered is very high. Therefore, a practical solution needs to be devised which can help alleviate the cost and delay associated with identification of a bug. In one of the standard practice followed by many semiconductor industries, a designer "sprinkles" some extra "spare gates" into the original circuit. These spare gates are not connected to the main circuit and are just lying around scattered throughout the chip. In an ideal situation of no bugs showing up ever, these gates serve no purpose. However, if a specific bug shows up in the chip after manufacturing and if the bug is fixable by using a few extra gates, such spare gates can come to rescue. The designer can connect these spare gates to make useful connections with the actual circuit and avoid adding any extra gate into the original design. Such changes in connections can be realized using changes in metal layers only and therefore, masks for only metal layers are to be regenerated. Avoiding the need to add additional gates can avoid regenerating the mask for the silicon layer, and thereby save a huge amount of cost as well as manufacturing time.
Functionally, no one needs spare gates - it is not useful for the end user, nor it is useful for the application developer. It is also an additional overhead for the chip designer to make sure that spare gates are properly isolated from the main circuit and do not introduce additional side-effects. The technology also does not demand addition of spare gates. However, spare gates find widespread usage in chip design owing to the economic benefits and quick release to market that they enable.
